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  • Electronics – Advanced Logic Synthesis

Electronics – Advanced Logic Synthesis

Curriculum

  • 1 Section
  • 34 Lessons
  • 10 Weeks
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  • Electronics - Advanced Logic Synthesis
    34
    • 2.1
      Mod-01 Lec-01 MOS Transistor
    • 2.2
      mod01lec02 MOS Transistor – Detailed Study
    • 2.3
      Mod-02 Lec-03 Combinational Circuits & layout
    • 2.4
      Mod-02 Lec-04 Delay
    • 2.5
      Mod-02 Lec-05 Sequential Circuits
    • 2.6
      Mod-02 Lec-06 Logical Effort
    • 2.7
      Mod-02 Lec-07 Circuit Families
    • 2.8
      Mod-03 Lab-1
    • 2.9
      Mod-03 Lab-2
    • 2.10
      Mod-03 Lab-3
    • 2.11
      Mod-03 Lab-4
    • 2.12
      Mod-03 Lec-08 Introduction to Synthesis
    • 2.13
      Mod-03 Lec-09 Libraries
    • 2.14
      Mod-03 Lec-10 RTL Coding for Synthesis
    • 2.15
      Mod-03 Lec-11 Reading Design in DC
    • 2.16
      Mod-03 Lec-12 Design Environment
    • 2.17
      Mod-03 Lec-13 Design Constraints
    • 2.18
      Mod-03 Lec-14 Compile Flow and stratergies
    • 2.19
      Mod-03 Lec-15 Analysis and Reporting
    • 2.20
      Mod-04 Lab-5
    • 2.21
      Mod-04 Lec-16 Advanced Synthesis Techniques
    • 2.22
      Mod-04 Lec-17 Datapath Extraction Guidelines
    • 2.23
      Mod-04 Lec-18 Power – Methodology and Analysis
    • 2.24
      Mod-05 Lab-6
    • 2.25
      Mod-05 Lab-7
    • 2.26
      Mod-05 Lab-8
    • 2.27
      Mod-05 Lab-9
    • 2.28
      Mod-05 Lec-19 Static Timing Analysis – Concepts and Flow
    • 2.29
      Mod-05 Lec-20 Interconnects and Delay calculation
    • 2.30
      Mod-05 Lec-21 Clock and Exceptions
    • 2.31
      Mod-05 Lec-22 On Chip Variation
    • 2.32
      Mod-05 Lec-23 Introduction to Crosstalk
    • 2.33
      Mod-05 Lec-24 Gaussian / Normal Distribution
    • 2.34
      Mod-05 Lec-25 Equivalence Checking / Formal Verification
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Mod-05 Lec-22 On Chip Variation
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Mod-05 Lec-24 Gaussian / Normal Distribution
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