Description: Electronics – Advanced Logic Synthesis
Curriculum
- 1 Section
- 34 Lessons
- 10 Weeks
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- Electronics - Advanced Logic Synthesis34
- 2.1Mod-01 Lec-01 MOS Transistor
- 2.2mod01lec02 MOS Transistor – Detailed Study
- 2.3Mod-02 Lec-03 Combinational Circuits & layout
- 2.4Mod-02 Lec-04 Delay
- 2.5Mod-02 Lec-05 Sequential Circuits
- 2.6Mod-02 Lec-06 Logical Effort
- 2.7Mod-02 Lec-07 Circuit Families
- 2.8Mod-03 Lab-1
- 2.9Mod-03 Lab-2
- 2.10Mod-03 Lab-3
- 2.11Mod-03 Lab-4
- 2.12Mod-03 Lec-08 Introduction to Synthesis
- 2.13Mod-03 Lec-09 Libraries
- 2.14Mod-03 Lec-10 RTL Coding for Synthesis
- 2.15Mod-03 Lec-11 Reading Design in DC
- 2.16Mod-03 Lec-12 Design Environment
- 2.17Mod-03 Lec-13 Design Constraints
- 2.18Mod-03 Lec-14 Compile Flow and stratergies
- 2.19Mod-03 Lec-15 Analysis and Reporting
- 2.20Mod-04 Lab-5
- 2.21Mod-04 Lec-16 Advanced Synthesis Techniques
- 2.22Mod-04 Lec-17 Datapath Extraction Guidelines
- 2.23Mod-04 Lec-18 Power – Methodology and Analysis
- 2.24Mod-05 Lab-6
- 2.25Mod-05 Lab-7
- 2.26Mod-05 Lab-8
- 2.27Mod-05 Lab-9
- 2.28Mod-05 Lec-19 Static Timing Analysis – Concepts and Flow
- 2.29Mod-05 Lec-20 Interconnects and Delay calculation
- 2.30Mod-05 Lec-21 Clock and Exceptions
- 2.31Mod-05 Lec-22 On Chip Variation
- 2.32Mod-05 Lec-23 Introduction to Crosstalk
- 2.33Mod-05 Lec-24 Gaussian / Normal Distribution
- 2.34Mod-05 Lec-25 Equivalence Checking / Formal Verification
