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- Design Verification & Test of Digital VLSI Circuits
Curriculum
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- 45 Lessons
- 10 Weeks
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- Design Verification & Test of Digital VLSI Circuits45
- 2.1Introduction to Digital VLSI Design Flow
- 2.2High Level Design Representation
- 2.3Transformations for High Level Synthesis
- 2.4Introduction to HLS: Scheduling, Allocation & Binding Problem
- 2.5Scheduling Algorithms Part 1
- 2.6Scheduling Algorithms Part 2
- 2.7Binding & Allocation Algorithms
- 2.8Two level Boolean Logic Synthesis Part 1
- 2.9Two level Boolean Logic Synthesis Part 2
- 2.10Two level Boolean Logic Synthesis Part 3
- 2.11Heuristic Minimization of Two-Level Circuits
- 2.12Finite State Machine Synthesis
- 2.13Multilevel Implementation
- 2.14Introduction to Formal Methods for Design Verification
- 2.15Temporal Logic: Introduction & Basic Operators
- 2.16Syntax & Semantics of CTL Part 1
- 2.17Syntax & Semantics of CTL Part 2
- 2.18Equivalence between CTL Formulas
- 2.19Introduction to Model Checking
- 2.20Model Checking Algorithms Part 1
- 2.21Model Checking Algorithms Part 2
- 2.22Model Checking with Fairness
- 2.23Binary Decision Diagram: Introduction & construction
- 2.24Ordered Binary Decision Diagram
- 2.25Operation on Ordered Binary Decision Diagram
- 2.26Ordered Binary Decision Diagram for State Transition Systems
- 2.27Symbolic Model Checking Introduction to Digital VLSI Testing
- 2.28Symbolic Model Checking
- 2.29Introduction to Digital VLSI Testing
- 2.30Functional & Structural Testing
- 2.31Fault Equivalence
- 2.32Fault Simulation Part 1
- 2.33Fault Simulation Part 2
- 2.34Fault Simulation Part 3
- 2.35Testability Measures (SCOAP)
- 2.36Introduction to Automatic Test Pattern Generation (ATPG) & ATPG Algebras
- 2.37D-Algorithm Part 1
- 2.38D-Algorithm Part 2
- 2.39ATPG for Synchronous Sequential Circuits
- 2.40Scan Chain based Sequential Circuit Testing Part 1
- 2.41Scan Chain based Sequential Circuit Testing Part 2
- 2.42Built in Self Test Part 1
- 2.43Built in Self Test Part 2
- 2.44Memory Testing Part 1
- 2.45